19th UK Asynchronous Forum

Imperial College London logo


Overview

The UK Asynchronous Forum is an informal 1-day meeting where those working in asynchronous design in the UK (and particularly research students) can meet to present and discuss ideas.  The event is optimised for UK participants though others are welcome to attend.  See the UK Asynchronous Forum home page for further details.

Scope

The scope of the Async Forum will be interpreted broadly to include:

  • clockless and multi-clocked systems
  • novel architectures with asynchronous dynamics
  • synchronization and metastability
  • communication-centric design for SoCs, NoCs
  • all sorts of timing issues in system and circuit design
  • variability analysis and variability-tolerance

and anything else relevant of interest.

Deadlines

  • 4th August, 2007 - submission deadline (will not be moved!)
  • 6th August, 2007 - registration deadline (will not be moved!)

Submissions

Extended abstracts of not more than 4 pages must be submitted to alex.yakovlev@newcastle.ac.uk by 4th August 2007.   Abstracts must be sent in either ASCII, postscript (which must be viewable with ghostview) or pdf.

Schedule

The general structure of the forum is below.

 

   Morning   

   Afternoon   

   Evening   

3rd September, 2007 (Monday)

travel

talks

dinner

4th September, 2007 (Tuesday)

talks

travel

 

Programme

The proceedings are available as a PDF: forum19.pdf.

Day 1 Monday, 3rd September 2007

13.00

Registration

13.30

Resolving deadlock failures in 2-phase interconnect
Yebin Shi and Steve Furber, University of Manchester

14.00

System-Level Model for a GALS Massively Parallel Multiprocessor
Mukaram Khan, Xin Jin, Steve B. Furber, Luis A. Plana, University of Manchester

14.30

Average Interconnections Delay Prediction for On-FPGA Communication Links
Terrence S.T. Mak, Pete Sedcole, Peter Y.K. Cheung and Wayne Luk, Imperial College London

15.00

Throughput-Centric Optimisation for fixed width Links with Crosstalk Avoidance Methods
Basel Halak, Alex Yakovlev, Newcastle University

15.30

Coffee

16.00

Avoiding Irreducable CSC Conicts in Component STGs
Dominic Wist, Ralf Wollowski, Hasso-Plattner-Institut fur Softwaresystemtechnik GmbH, Potsdam, Germany

16.30

Conditional Partial Order Graphs and Dynamically Recongurable Control Synthesis
Andrey Mokhov and Alex Yakovlev, Newcastle University

17.00

Relative Timing Applied to Asynchronous Circuit Synthesis and Decomposition
Yu Li, Alex Yakovlev, Newcastle University

17.15

Refined Delay Model for Geometric Program-based Delay Optimization
Ping Wang, Alex Yakovlev, Newcastle University

17.30

Presentation by attendees

17.45

Business Meeting

19.30

Forum Dinner

Day 2 Tuesday, 4th September 2007

09.00

High Performance Asynchronous Circuit Design Method and Application
Charlie Brej, University of Manchester

09.30

Architectural enhancements for a synthesised self-timed processor
L. A. Tarazona, L.A. Plana, and D. A. Edwards, University of Manchester

10.00

Automatic Buffer Insertion in Balsa-synthesised Asynchronous Circuits
L. A. Tarazona, D. A. Edwards, University of Manchester

10.30

High-level model verification within Workcraft Framework
Ivan Poliakov, Andrey Mokhov, Danil Sokolov, Alex Yakovlev, Newcastle University

11.00

Coffee

11.30

Variability analysis of a high performance strained silicon Jamb latch synchronizer
H. Ramakrishnan, S. Shedabale, J. Zhou, G. Russell, and A. Yakovlev, Newcastle University

12.00

On-chip Measurement of MTBF for A Robust Synchronizer
Jun Zhou, David Kinniment, Gordon Russell, and Alex Yakovlev, Newcastle University

12.30

Implementation and Testing Asynchronous Circuits with the Aid of Programmable Devices
Nikolaos Minas, Matthew Marshall, Gordon Russell, Newcastle University

13.00

Power Management with Accumulation and Fire Mechanism
Yuan Chen, Fei Xia, Delong Shang, Alex Yakovlev, Newcastle University

13.30

Close

Location

The 19th UK Asynchronous Forum is being hosted by the Circuits and Systems Group at the Department of Electrical and Electronic Engineering, Imperial College London.

Room details : Room 611, Gabor Seminar Room, Electrical Engineering Building, South Kensington Campus (Map).

Day 1 evening meal will be at 170 Queen's Gate.

Transpotation

From Heathrow airport

Take the Underground train (Piccadilly Line) to South Kensington station (50 minutes travelling time).

From Gatwick airport

Take a British Rail train to Victoria station (journey time 40 minutes) and then by Underground train (Circle or District Line; westbound) to South Kensington.

Both airports are some distance from central London and a taxi is not recommended for the whole journey. However, if you have to do so, establish the cost before you get in.

On foot

From South Kensington station, the campus is only five minutes' walk. Either follow the subway signposted to the museums or walk north up Exhibition Road. The College is next to the Science Museum.

By car

Car parking at the South Kensington campus is severely restricted and you are advised NOT to bring a car unless permission has been given. After 6pm, at weekends and during vacations the car park is open to the paying public. Parking in the streets surrounding the College is at pay and display or parking meters for limited periods only.

Travel Guides and Maps

Registration and Accommodation

Registration form . Payment will be cheque only to "Imperial College Science, Technology and Medicine" .

Accommodation will be at Wigram House, Victoria.

Cost

Workshop fee (including proceedings, dinner and accomodation at Wigram House) is £65.00 per person.

Workshop fee without accomodation will be £35.00 per person. You will have to make your own accomodation arrangements.

Contacts

Programme organiser:  

Alex Yakovlev  

(alex.yakovlev@newcastle.ac.uk)

Local organisers:  

Peter Cheung 

(p.cheung@imperial.ac.uk)

  

Terrence Mak

(t.mak@imperial.ac.uk)


 


UK Async Forum Home Page | Circuits and Systems Group | Department of Electrical and Electronic Engineering


Last Update July 2007