Ben Cope's Home Page

I am a PhD Student in the Circuits and Systems Group which is part of the Department of Electrical and Electronic Engineering at Imperial College London. This homepage contains a brief Curriculum Vitae and a summary of my research interests. Thank you for taking the time to read through my interests and work, please contact me at details below with any comments or suggestions.

Dept. Electrical and Electronic Engineering
Imperial College London
South Kensington campus
London SW7 2BT, United Kingdom

Phone: +44 (0) 20 7954 6336
Fax: +44 (0) 20 7581 4419

Email: benjamin.cope at

On this page:

Academic History

[2004-date] Imperial College London. PhD Reconfigurable Computing, Circuits and Systems, EEE
[2000-2004] Imperial College London. 1st Class Masters Degree in Electronic and Electrical Engineering (Technical Stream)
[1998-2000] Runshaw College, Leyland. A-Levels in Mathematics (A), Physics (B) and Computing (A)
[1993-1998] Southlands High School, Chorley. GCSEs in Double Award Science (A*A*), Mathematics (A), English Literature (B) and Language (B), Geography (A), History (A), Information Technology (A), French (B) and Food Technology (B).

Research Interests

My general area of interest is the field of Reconfigurable Computing. Focusing specifically on the use of FPGAs (Field Programmable Gate Arrays) and GPUs (Graphics Processing Units) for Video Processing.
My area of interest is broadly termed as Reconfigurable Systems for Video Processing. Under this broad title I have specifically been looking at the application of Graphics Processing Units (GPUs) to tasks currently approached with Field Programmable Gate Arrays (FPGAs.) My work has focused on algorithms for Primary Colour Correction and 2D Convolution Filtering (reports for which are given below.) I have also looked at Image Resizing (bi-cubic and filtering methods) to analyse the percieved quality difference and consider how each is implemented.
I am currently supported by: the Donal Morphy Scholarship, the Engineering and Physical Sciences Research Council and Sony Broadcast and Professional Research Labs.

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Work Experience

[Summer 2001] BAE Systems. Placement work in departments of Mechanical Engineering, Product Support, Digital, Radio Frequency & Microwave and Software.
[Summer 2002] AMS Ltd. Placement work in departments of Systems and Technical Services.
[Summer 2003] AMS Ltd. Placement work in departments of Test and Digital.


[Oct 2004] IEE Prize. For Excellence over 4 Years of Undergraduate Study on Technical Stream.
[2003-2004]IEC Everitt Award. For Excellent Performance in the field of EEE.
[Oct 2003] Sir William Siemens Medal. Recognition of Academic Excellence and Outstanding Achievement in Summer Placement, awarded in the 3rd Year of Undergraduate Study.


Swimming and Waterpolo - With the Imperial College Swimming Club. During the 2005/2006 season I was the social secretary and was one of the main organisers of a sucessful waterpolo tour to Croatia in Summer 2006.
Hiking - Completed Long Distance Trails including Wainwrights Coast to Coast and most recently the West Highland Way.
Long Distance Running - Fastest Marathon time 3hrs 31mins (Rome 2006) and Half Marathon 1hr 28mins (Blackpool 2006). Run as a member of the Serpentine Running Club.
Ultimate Frisbee - Monday Evening Social Games in Hyde Park


`Have GPUs made FPGAs redundant in the field of video processing?', B. Cope, P.Y.K. Cheung, W. Luk and S. Witt, Proc. IEEE International Conference on Field-Programmable Technology 2005, p.p. 111--118, Dec 2005. [Link]

`Can GPUs be used to improve video processing systems?', B. Cope, Proc. 16th IEEE International Conference on Field Programmable Logic and Applications 2006 (PHD Forum)

`Bridging the gap between FPGAs and multi-processor architectures: A video processing perspective', B. Cope, P.Y.K. Cheung and W. Luk, Proc. 18th IEEE International Conference on Application Specific Systems, Architectures and Processors 2007

`Using reconfigurable logic to optimised GPU memory accesses', B. Cope, P.Y.K. Cheung and W. Luk, Proc. 11th ACM/SIGDA Design, Automation and Test in Europe Conference 2008


Implementation of Primary Colour Correction on GPUs, FPGAs and a CPU
Implementation of 2D Convolution on FPGAs, GPUs and a CPU
6 Month Technical Report (April 2005)
PhD to MPhil Transfer Report (December 2005)
Progress Report Summer 2006

Refereneced Code

Code referenced in paper "Have GPUs made FPGAs redundant in the field of Video Processing?" Implementations of Primary Colour Correction on GPU, FPGA and CPU
Implementations of 2D Convolution on GPU, FPGA and CPU

[These pages are currently under reconstruction]