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Welcome to Chakkapas' home page. I am a research student under supervision of Prof.Peter Cheung and Prof. Wayne Luk. My research aim is to enable large system to run on limited FPGA multiplication resources. Now a day larger FPGA chips contain number of embedded multipliers but it is not guarantee that it is enough for large-size applications. One way is to find bigger chips. Alternately is to find some methods to fit it in.

Publication
1. Chakkapas Visavakul, Peter Cheung, Wayne Luke, "A Digit-Serial Structure for Reconfigurable Multipliers" in Proceedings of 11th International Conference on Field Programmable Logic and Application (FPL2001), pages 565-573, August 2001.

Contact:
Mr. Chakkapas Visavakul

Mailstop: EEE-CAS
Department of EEE
Imperial College
Exhibition Road
London
SW7 2BT
c.visavakul at imperial.ac.uk

Misc:

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