This page has the source code for the paper "FPGA-Optimised Uniform Random Number Generators using LUTs and Shift Registers" which was presented at FPL 2010. The idea of the paper was to design uniform random number generators for FPGAs which provide all of the following properties:
This page provides the same LUT-SR generators described in the paper, but as directly usable VHDL which you can (hopefully) just drop into a project.
I realised putting source code in a paper was risky, but never mind. Anyway, so far I have found one small bug in the paper, but as it is related to retrieving state from the RNG, and only affects the simulator (not the VHDL), it shouldn't affect anyone. Anwyay, in Listing 1 of the published paper the line:
int s_out=cs[perm[seedTap]];should actually be:
int s_out=cs[cycle[seedTap]];This only affects the software simulator (everywhere else the correct index was used).
In the version 2 release I forgot a "#include stdlib.h" so under some compilers it gave an error, but apart from that there are no changes between 2 and 3.