WORKSHOP W2: IMPACT OF PROCESS VARIABILITY ON DESIGN AND TEST


Welcome to Workshop W2. On this page you can download the material associated with the workshop, including slides from the talks and abstracts of the posters.

WORKSHOP DIGEST

Click here to downloaded the complete digest in a single PDF file (23MB). Slides of the each presentation and the poster abstracts are also available to download as individual files below.

KEYNOTE AND INVITED TALKS

Time Title
0830 Welcome and introduction
0840 KEYNOTE - Managing Variations: from Devices to Systems, Sandip Kundu, University of Massachusetts, Amherst, US
0930 Variability Aware Power and Timing Modeling of SoCs, Miguel Miranda, Technology Aware Design Group, IMEC, BE
1110 Model to Hardware Matching for Nanometer-scale Technologies, Sani Nassif, IBM Austin Research Laboratory, US
1140 Variability and FPGAs - Disaster or Opportunities?, Peter Cheung, Imperial College London, UK
1310 Fault Tolerant Architectures for Mitigating Variability Issues, Michael Nicolaidis, TIMA Laboratory, FR
1340 Distinguishing Critical and Non-Critical Variation in Nanometer Technology, Rob Aitken, ARM, US
1410 Statistical Compact Modelling as a Tool in Understanding Circuit Variability, Scott Roy, Glasgow University, UK

POSTERS

Title
NBTI Degradation and Resilient Circuit Design, Peter Glösekötter, University of Applied Sciences, Münster, DE; Mladen Berekovic, Technical University of Braunschweig, DE; Gilson I. Wirth, UFRGS, BR
Statistical Variability Analysis of a Mutual Exclusion Element for Strained Silicon Processes, Hiran K Ramakrishnan, S. Shedabale, G. Russell, and Alex Yakovlev, Newcastle University, UK
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design, Giacomo Paci, IMEC, BE, and University of Bologna, IT; Axel Nackaerts, IMEC, BE; Francky Catthoor, IMEC, BE; Luca Benini, DEIS, University of Bologna, IT; Pol Marchal, IMEC, BE
AHMOSE: Towards a Circuit Level Solution for Process Variability, Eslam Yahya, TIMA, FR, and Banha High Institute of Technology, EG; Marc Renaudin, TIMA, FR
Simulation of Intrinsic Parameter Fluctuation in CMOS - The link between Physical Devices and Circuits, Binjie Cheng, Scott Roy, and Asen Asenov, University of Glasgow, UK
Fast and accurated approximation of marginal probabilities, Christoph Sohrmann, Lutz Muche, and Joachim Haase, EAS Dresden, DE
Statistical Circuit Simulation with the Effect of Random Discrete Dopants in Nanometer MOSFET Devices, Noor Ain Kamsani, Binjie Cheng, Scott Roy, and Asen Asenov, University of Glasgow, UK
Meeting the Design Challenges of nano-CMOS Electronics, Campbell Millar, et al, University of Glasgow, UK