Vassilis Androutsopoulos

Research student

sponsors LSI LOGIC

Supervised by Dr T.J.W Clarke

Co supervised by D.M Brookes and P.Y.K Cheung

Circuit and Systems group

Department of Electrical and Electronic Engineering

Imperial College

tel: (020)7594-6336

Research Interests

  • VLSI Architectures for Video Processing

  • Formal Specification methods for High-level Synthesis

  • Protocol Conversion methods between Hardware interfaces

  • Timing constraint derivations and specifications

  • Design Automation

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    PUBLICATIONS

  • Androutsopoulos, V., Clarke, T. J. W., and Brookes, M. Synthesis and Optimisation of Interfaces Between Hardware Modules with incompatible Protocols, paper presented at IEEE International Symposium on Circuits & Systems, Bangkok, Thailand, May 2003

  • Clarke, T. J. W. and Androutsopoulos, V. Protocol Converter Synthesis, September 2003, IEE Journal (accepted)

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    Research links and member Societies

  • Member of SIGDA (UK)

  • Association of Computing Machinery

  • Institution of Electrical and Electronic Engineers

  • European Design and Automation Society

  • Research Index Citeseer

  • Imperial College IEE and IEEE publications

    • HW SW Codesign, Embedded Systems, HLS and CAD WEB pages

  • Cadpages UC

  • HW SW codesign tools

    • Other Interests and CV

  • Orchestral music, opera

  • Tennis, athletics, martial arts

  • CV available upon request

    • Recent Pics