Felix Winterstein

Felix Winterstein This website summarises my research in the Circuits and Systems Group at Imperial College London.
Most of my research addresses digital computation using FPGAs and high-level synthesis.

I have moved to a new position in the start-up Xelera Technologies to build FPGA IP for tomorrow's data centres.
https://xelera.io/

My CV

Publications

Please note that the official versions of the preprints listed here are copyright IEEE, ACM, or Springer.

2017

Felix Winterstein, George Constantinides: "Pass a Pointer: Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs," in Proc. International Conference on Field-Programmable Technology (ICFPT), 2017. [acceptance rate 23%] paper
Felix Winterstein: "Separation Logic for High-level Synthesis," Springer, 2017, ISBN 978-3-319-53222-6. book
Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie Chen, Michael Adler, Joel Emer: "Automatic Construction of Program-Optimized FPGA Memory Networks," in Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA), 2017. [acceptance rate 25%] paper
Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Michael Adler, Joel Emer: "(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies," in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2017. paper

2016

Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, George Constantinides: "Custom Multi-Cache Architectures for Heap Manipulating Programs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016. paper
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel Emer: "LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning," in Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA), 2016. [acceptance rate 27%] paper
Nadesh Ramanathan, John Wickerson, Felix Winterstein, George Constantinides: "A Case for Work-stealing on FPGAs with OpenCL Atomics," in Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA), 2016. [acceptance rate 27%] paper
Shane Fleming, David Thomas, Felix Winterstein: "A Power-Aware Adaptive FDIR Framework using Heterogeneous System-on-chip Modules," book chapter in "FPGAs and Parallel Architectures for Aerospace Applications", pp. 75-90, Springer, 2016, ISBN 978-3-319-14352-1. book chapter

2015

Felix Winterstein, Samuel Bayliss, George Constantinides: "Separation Logic for High-Level Synthesis," in ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2015. paper
Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson, George Constantinides: "Custom-Sized Caches in Application-Specific Memory Hierarchies," in Proc. International Conference on Field-Programmable Technology (ICFPT), 2015. [acceptance rate 21%] paper
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel Emer: "Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies," in Proc. International Conference on Field Programmable Logic and Applications (FPL), 2015. [acceptance rate 22%] paper
Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides: "MATCHUP: Memory Abstractions for Heap Manipulating Programs," in Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA), 2015. [acceptance rate 26%] paper

2014

Felix Winterstein: "Simultaneous Transmission of GMSK Telemetry and PN Ranging: Measurement Report in Support of the Draft CCSDS Recommendations 401(2.4.22A) and 401(2.4.22B)," in Proc. Fall Meeting of the Consultative Committee for Space Data Systems (CCSDS), 2014. [acceptance rate unknown] paper
Eduardo Aguilar Pelaez, Samuel Bayliss, Alex Smith, Felix Winterstein, Dan Ghica, David Thomas, George Constantinides: "Compiling Higher Order Functional Programs to Composable Digital Hardware," in Proc. IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014. paper
Felix Winterstein, Samuel Bayliss, George A. Constantinides: "Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis," in Proc. IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014. (best paper candidate) [acceptance rate 16%] paper

2013

Felix Winterstein, Samuel Bayliss, George A. Constantinides: "High-Level Synthesis of Dynamic Data Structures: A Case Study Using Vivado HLS," in Proc. International Conference on Field-Programmable Technology (ICFPT), 2013. [acceptance rate 21% (46% short)] paper
Felix Winterstein, Samuel Bayliss, George A. Constantinides: "FPGA-based K-means Clustering Using Tree-Based Data Structures," in Proc. International Conference on Field Programmable Logic and Applications (FPL), 2013. [acceptance rate 23%] paper

2012

Felix Winterstein, Gunther Sessler, Maria Montagna, Magdalena Mendijur, Guillaume Dauron, Piermario Besso: "Scalable Front-End Digital Signal Processing for a Phased Array Radar Demonstrator," in Proc. International Radar Symposium (IRS), 2012. (received distinction) [acceptance rate unknown] paper

2011

Gunther Sessler, Magdalena Martinez, Maria Montagna, Alberto Martin, Felix Winterstein, Guillaume Dauron, Piermario Besso: "Design and Implementation of a Low Power Mini-Radar Demonstrator," in Proc. European Space Surveillance Conference (ESSC), 2011. [acceptance rate unknown]

Talks

Separation Logic for High-level Synthesis, University College London 2015, seminar talk slides
MATCHUP: Memory Abstractions for Heap Manipulating Programs, FPGA 2015, conference talk slides
STeffiHLS: Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis, Harvard University 2014, seminar talk slides
Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis, FCCM 2014, conference talk slides
FPGA-based K-means Clustering Using Tree-Based Data Structures, FPL 2013, conference talk slides
High-Level Synthesis of Dynamic Data Structures: A Case Study Using Vivado HLS, FPT 2013, poster poster
Separation Logic and its application to HLS, Imperial College 2012, seminar talk slides
Scalable Front-End Digital Signal Processing for a Phased Array Radar Demonstrator, IRS 2012, conference talk slides

PhD Thesis

"Separation Logic for High-Level Synthesis", April 2016 thesis
Book version: Springer Theses

Space

OPS-SAT: How will commercial FPGAs cope in space? Our OPS-SAT experiment. Here is our OPS-SAT blog

Open source

We have open sourced the OpenCL 2.0 Shared Virtual Memory framework for FPGAs (described in the ICFPT'17 paper). The code is available on GitHub: FPGA-shared-mem
We have open sourced code examples in support of the tutorial "The LEAP Run-time System – Rapid System Integration of Your HLS Kernels", held at the International Conference on Field-programmable Logic and Applications 2015. The tutorial explains how to connect HLS kernels to Intel/MIT's LEAP environment. The code is available on GitHub: LEAP-HLS. Slides are here.
We have open sourced a high-level synthesis case study comparing the implementations of two K-means clustering algorithms. The code may also provide useful hints of how to squeeze performance out of Xilinx' Vivado HLS by source code refactoring. The code is available on GitHub: Vivado-KMeans

Consultancy

Contact me.

News

Tweets by @fewinterstein

Getting in touch

Please contact me on my College email address f.winterstein12_at_imperial.ac.uk (replace _at_ with @).
My office address is:: Felix Winterstein; Department of Electrical and Electronic Engineering; Imperial College London; South Kensington Campus, London SW7 2BT; United Kingdom