Stylianos I. Venieris and Christos Savvas Bouganis
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs, FCCM 2016
(link, paper, slides, bibtex)
This paper presents the Synchronous Dataflow (SDF) modelling core of fpgaConvNet and the automated design methodology for the generation of high-throughput hardware mappings . High-throughput applications allow the use of batch processing and offer opportunities for optimisations. To this end, fpgaConvNet uses a set of transformations over the SDF model, including FPGA reconfiguration, coarse-grained folding and fine-grained folding in order to traverse the large architectural design space and yield an optimised, high-throughput design for the target FPGA platform.